#2.1 Designing for Performance #2.2 Microprocessor Speed #2.3 Problems with Clock Speed and Logic Density #2.4 Multicore #2.5 Many Integrated Core (MIC) Graphics Processing Unit (GPU) #2.6 Amdahl's Law #2.7 Little’s Law

#3.1 Computer Components #3.2 Instruction Fetch and Execute #3.3 Detailed look at the basic instruction cycle #3.4 Interrupts #3.5 Instruction cycle with interrupts #3.6 I/O Function #3.7 Bus interconnection #3.8 The most important types of control lines #3.9 Point-to-Point Interconnect #3.10 QPI Link Layer #3.11 Peripheral Component Interconnect (PCI) #3.12 PCIe-Transaction Layer (TL)

#4.1 cash-1 #4.2 Cach-2 #4.3 cache-3 #4.4 cach-4 #4.5 cache-5 #4.6 Replacement Algorithms #4.7 Line size

#5.1 Internal Memory #5.2 Read Only Memory (ROM) #5.3 Volatile Memory #5.4 SRAM versus DRAM #5.5 Organisation in detail (2) #5.6 Memory Modules- Memory Chips #5.7 Internal Memory -exercies #5.8 EXERCISE

#6.1 تمارين1 #6.2 تمارين-2

#7.1 Magnetic Disk-Hard Disk #7.2 Magnetic Disk- Hard Disk A sector Format #7.3 1-RAID #7.4 RAID Comparison #7.5 Optical Disk (CD & DVD) #7.6 Dual layer DVD ROM

#8.1 Input/Output #8.2 I/O Commands #8.3 Interrupt Driven I/O #8.4 Direct Memory Access (DMA)

#9.1 Pipelining #9.2 Data Hazards

#10.1 Processor organization #10.2 Program Status Word(PSW)

#11.1 fetch and execute-ex-mid1 #11.2 clock rate -ex #11.3 Average CPI -ex1 #11.4 average CPI -ex #11.5 computers is faster -ex #11.6 CPU time-ex #11.7 CPU time example #11.8 mid1-instruction word example #11.9 mid1-descriptions of the instructions ex #11.10 mid1-execution instructions ex #11.11 mid1-excode #11.12 CPU time example #11.13 Direct Memory #11.14 four-way set-associative #11.15 direct-mapped cache-ex #11.16 32 way set associative cache-ex #11.17 fully associative cache. #11.18 direct mapped #11.19 mid1-match #11.20 Design memory-final #11.21 mid1-code-ex #11.22 Design momery #11.23 Build memory #11.24 pipelined processor #11.25 pipelined processor - السؤال السابق حل الدكتور #11.26 mid1-Featch and excute #11.27 أختياري - Mid1 #11.28 أختياري-ميد1 #11.29 mid1-َQuiz #11.30 أختياري #11.31 direct mapped-mid #11.32 أختياري-mid #11.33 أختياري-mid #11.34 true and false #11.35 match #11.36 memory map #11.37 Buses #11.38 memory #11.39 Featch and excute #11.40 Instruction memory #11.41 accesstime #11.42 build memory

#12.1 Response Time and Throughput #12.2 Instruction Count and CPI #12.3 Question2 #12.4 CPI in More Detail #12.5 Reducing Power

#13.1 Fetch #13.2 Rules for Clock Cycle Grouping #13.3 Control of the processor #13.4 Control Signals - output #13.5 Internal Organization #13.6 Timing Diagram for Intel 8085 OUT Instruction