#2.1 Designing for Performance #2.2 Microprocessor Speed #2.3 Problems with Clock Speed and Logic Density #2.4 Multicore #2.5 Many Integrated Core (MIC) Graphics Processing Unit (GPU) #2.6 Amdahl's Law #2.7 Little’s Law #2.8 Pipelining #2.9 Data Hazards

#3.1 Computer Components #3.2 Instruction Fetch and Execute #3.3 Detailed look at the basic instruction cycle #3.4 Interrupts #3.5 Instruction cycle with interrupts #3.6 I/O Function #3.7 Bus interconnection #3.8 The most important types of control lines #3.9 Point-to-Point Interconnect #3.10 QPI Link Layer #3.11 Peripheral Component Interconnect (PCI) #3.12 PCIe-Transaction Layer (TL)

#4.1 cash-1 #4.2 Cach-2 #4.3 cache-3 #4.4 cach-4 #4.5 cache-5 #4.6 Replacement Algorithms #4.7 Line size

#5.1 Internal Memory #5.2 Read Only Memory (ROM) #5.3 Volatile Memory #5.4 SRAM versus DRAM #5.5 Organisation in detail (2) #5.6 Memory Modules- Memory Chips #5.7 Internal Memory -exercies #5.8 EXERCISE

#6.1 تمارين1 #6.2 تمارين-2

#7.1 Magnetic Disk-Hard Disk #7.2 Magnetic Disk- Hard Disk A sector Format #7.3 1-RAID #7.4 RAID Comparison #7.5 Optical Disk (CD & DVD) #7.6 Dual layer DVD ROM

#8.1 Input/Output #8.2 I/O Commands #8.3 Interrupt Driven I/O #8.4 Direct Memory Access (DMA)

#9.1 Processor organization #9.2 Program Status Word(PSW)

#10.1 fetch and execute-ex-mid1 #10.2 mid1-clock rate -ex #10.3 mid1-Average CPI -ex1 #10.4 mid1-average CPI -ex #10.5 mid1-computers is faster -ex #10.6 CPU time-ex #10.7 CPU time example #10.8 mid1-instruction word example #10.9 mid1-descriptions of the instructions ex #10.10 mid1-execution instructions ex #10.11 mid1-excode #10.12 mid1-CPU time example #10.13 Direct Memory #10.14 four-way set-associative #10.15 direct-mapped cache-ex #10.16 32 way set associative cache-ex #10.17 fully associative cache. #10.18 direct mapped #10.19 mid1-match #10.20 Design memory-final #10.21 mid1-code-ex #10.22 Design momery #10.23 Build memory #10.24 mid1-pipelined processor #10.25 pipelined processor - السؤال السابق حل الدكتور-mid1 #10.26 mid1-Featch and excute #10.27 أختياري - Mid1 #10.28 أختياري-ميد1 #10.29 mid1-َQuiz #10.30 أختياري #10.31 direct mapped-mid2 #10.32 أختياري-mid #10.33 أختياري-mid #10.34 true and false #10.35 match #10.36 memory map #10.37 Buses #10.38 memory #10.39 Featch and excute #10.40 mid1-Instruction memory #10.41 accesstime #10.42 build memory #10.43 CPI-Mid1 #10.44 mid1-Code #10.45 Memory instraction - mid1 #10.46 mid1-Code #10.47 Code-mid1 #10.48 mid1-اختياري #10.49 ode #10.50 code #10.51 Hit ratio #10.52 memory capacity #10.53 memory #10.54 memory #10.55 building memory #10.56 أختياري-mid1 #10.57 mid1-code #10.58 أختياري-mid1 #10.59 code-mid1 #10.60 pipelined processor -mid1 #10.61 microoperation-mid2 #10.62 microoperation-mid2 #10.63 microoperation-mid2 #10.64 microoperation-mid2 #10.65 microoperation-mid2 #10.66 final part1 #10.67 final part2

#11.1 Response Time and Throughput #11.2 Instruction Count and CPI #11.3 Question2 #11.4 CPI in More Detail #11.5 Reducing Power

#12.1 Fetch #12.2 Rules for Clock Cycle Grouping #12.3 Control of the processor #12.4 Control Signals - output #12.5 Internal Organization #12.6 Timing Diagram for Intel 8085 OUT Instruction