#2.1 SR-flip-flop #2.2 D Latch #2.3 Edge-triggered D flip-flop #2.4 JK Flip-Flop #2.5 T Flip-Flop

#3.1 Register #3.2 Shift Registers #3.3 Serial Adder using JK FFs #3.4 Universal Shift Register #3.5 4-bit binary counter #3.6 bit Up/Down Binary Counter #3.7 BCD Counters #3.8 4-bit binary counter with parallel load #3.9 Generate any count sequence

#4.1 Q1 #4.2 Q2 #4.3 Q3 #4.4 Q4 #4.5 Q5 #4.6 mid1-Shift question1 #4.7 mid1-Shift question2 #4.8 Universal Shift Register #4.9 mid1-Exercises-Revision #4.10 mid1-Counter #4.11 mid1-S-R Flip-flop Time Switching Diagram #4.12 Sheet 3 -Q1 #4.13 Sheet 3 -Q3,4,5 #4.14 Sheet 3 -Q6 #4.15 Sheet 3 -Q7 #4.16 k-map #4.17 k-map-2 #4.18 mid1-Draw the Q waveform #4.19 mid1-counter #4.20 Shift register-mid1 #4.21 mid1 #4.22 أختياري-1 mid #4.23 mid1 #4.24 mid1 #4.25 mid1 #4.26 Counter #4.27 reduced state diagram #4.28 2 bits counter #4.29 next state equations JK- flip flops #4.30 Design a combinational circuit using ROM #4.31 Counter from 0 to 3

#5.1 State Equations #5.2 Analysis with D FFs #5.3 Analysis with JK Flip-Flops #5.4 Analysis with T Flip-Flops #5.5 State Reduction #5.6 State Assignment #5.7 Synthesis using D flip-flops #5.8 Synthesis using JK FFs #5.9 Synthesis using T flip-flops

#6.1 sheet1 #6.2 sheet2

#7.1 Memory and Programmable Logic #7.2 Read Only Memory #7.3 Combinational Programmable Devices